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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PRELIMINARY
Some of contents are described for general products and are subject to change w ithout notice.
DESCRIPTION
M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
FEATURES
M2V64S20/30/40DTP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle T ime Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Max.) (Single Bank) (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) V64S20D V64S30D V64S40D Icc6 Self Refresh Current (Max.) -6 7.5ns 45ns 20ns 5.4ns 67.5ns 75mA 75mA 85mA 1mA -7 10ns 50ns 20ns 6ns 70ns 70mA 70mA 80mA 1mA -8 10ns 50ns 20ns 6ns 70ns 70mA 70mA 80mA 1mA
- Single 3.3v0.3V power supply - Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2> - Fully Synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0 & BA1 (Bank Address) - /CAS latency- 2 and 3 (programmable) - Burst length- 1, 2, 4, 8 and full page (programmable) - Burst type- sequential and interleave (programmable) - Byte Control- DQM L and DQMU for M2V64S40DTP - Random column access - Auto p recharge and All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles every 64ms - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PIN CONFIGURATION (TOP VIEW) M2V64S20DTP M2V64S30DTP M2V64S40DTP
PIN CONFIGURATION (TOP VIEW)
Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
CLK CKE /CS /RAS /CAS /WE DQ0-15
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O
DQM A0-11 BA0,1 Vdd VddQ Vss VssQ
: Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
DQ0-7
BLOCK DIAGRAM
I/O Buffer
Memory Array
4096 x512 x8 Cell Array
Memory Array
4096 x512 x8 Cell Array
Memory Array
4096 x512 x8 Cell Array
Memory Array
4096 x512 x8 Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Note : This figure shows the M2V64S30DTP. The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3. The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15.
Type Designation Code
These rules are only applied to the Synchronous DRAM family.
M2 V 64 S 3 0 D TP -8
Access Item -6 : 7.5ns (PC133 3-3-3), -7 : 10ns (PC100 2-2-2), -8 : 10ns (PC100 3-2-2) T P : T S O P (II) D : 5th gen. R eserved for Future Use 2 : x4, 3 : x8, 4 : x16
P ackage T ype P rocess Generation Function Organization Synchronous DRAM Density Interface Mitsubishi DRAM
64 : 64Mbit V : LVT T L
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / selfrefresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9 (x4) / A0-8 (x8) / A0-7 (x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Input / Output
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-11
Input
BA0,1
Input
DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) DQM(x4,x8), DQM(U, L)(x16)
Input
Din Mask and Output Disable: When DQM(U, L) is high in burst write, Din for the current cycle is masked. When DQM(U, L) is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only.
Vdd, Vss VddQ, VssQ
Power Supply Power Supply
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
BASIC FUNCTIONS
The M 2V64S20, 30 and 40DTP provides basic functions, bank (row) activate, burst read and write, bank (row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Ref resh Option @ref resh command Precharge Option @precharge or read/write command def ine basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge,READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-p recharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry MNEMONIC DESEL NOP ACT PRE PREA WRITE WRITEA READ READA REFA REFS CKE CKE n-1 n H H H H H H H H H H H L Self-Refresh Exit REFSX L Burst Terminate Mode Register Set TBST MRS H H H X X L L L H H L H H L H L L X X L X X L X X L X X V*1 X X X X X X X X X H L H /CS /RAS /CAS /WE BA0,1 A11 H L L L L L L L L L L H X H L L L H H H H L L X X H H H H L L L L L L X X H H L L L L H H H H X X X V V X V V V V X X X X X V X X V V V V X X X A10 A0-9 X X V L H L H L H X X X X X V X X V V V V X X X
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State IDLE /CS H L L L L L L L ROW ACT IVE H L L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H H H L L L L X H H L H H L L X H H L L H H L L X H L X H L H L X H L H L H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 Command Action DESEL NOP TBST READ & WRITE ACT PRE & PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL
READ & READA WRITE & BA, CA, A10 WRITEA BA, RA BA, A10 X Op-Code, Mode-Add ACT PRE & PREA REFA MRS
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State READ /CS H L L L L L L L L WRITE H L L L L L L L L /RAS /CAS /WE Address X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Action DESEL NOP TBST READ /READA NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3
WRITE & Terminate Burst, Latch CA, Begin WRITEA Write, Determine Auto-Precharge*3 ACT PRE & PREA REFA MRS DESEL NOP TBST READ & READA WRITE & WRITEA ACT PRE & PREA REFA MRS Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State READ with AUTO PRECHARGE /CS H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L /RAS /CAS /WE Address X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Action DESEL NOP TBST READ & READA WRITE & WRITEA ACT PRE & PREA REFA MRS DESEL NOP TBST READ & READA WRITE & WRITEA ACT PRE & PREA REFA MRS NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Action DESEL NOP TBST READ & WRITE ACT PRE & PREA REFA MRS DESEL NOP TBST NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ & ILLEGAL*2 WRITE ACT PRE & PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State WRITE RECOVERING /CS H L L L L L L L REFRESHING H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Action DESEL NOP TBST READ & WRITE ACT PRE & PREA REFA MRS DESEL NOP TBST READ & WRITE ACT PRE & PREA REFA MRS NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State MODE REGISTER SETTING /CS H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H L H H L L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Action DESEL NOP TBST READ & WRITE ACT PRE & PREA REFA MRS NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add Action X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER SET
MRS
IDLE
REFA
AUTO REFRESH
CKEL
CLK SUSPEND
ACT CKEL CKEH
CKEH
POWER DOWN
ROW ACTIVE
TERM WRITE WRITEA READA READ WRITE TERM READ
WRITE SUSPEND
CKEL
CKEL
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA READA
READA
WRITEA SUSPEND
CKEL
CKEL
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. M aintain stable power, stable clock, and NOP input conditions for a minimum of 200s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type, /CAS Latency and Write M ode can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE
V
BA0,1 A11-A0 BA0 BA1 A11 A10 A9 0 0 0 0 WM A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 BL A0
LTMODE
Write Mode
0 1
Burst Write Single Write 0 0 0 0 1 1 1 1
BL 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
LATENCY MODE
CL 000 001 010 011 100 101 110 111
/CAS LATENCY R R 2 3 R R R R
BURST LENGTH
BT=0 1 2 4 8 R R R Full Page
BT=1 1 2 4 8 R R R R
BURST TYPE
SEQUENTIAL INTERLEAVED
R: Reserved for Future Use
MITSUBISHI ELECTRIC
15
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
CLK Command Address DQ /CAS Latency CL= 3 BL= 4 Burst Length Burst Type Burst Length
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 1 2 2 3 0 1 3 0 1 0 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
MITSUBISHI ELECTRIC
16
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-11. M ultiple banks can be active state concurrently by issuing multiple ACT commands. M inimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. M inimum delay of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=2)
CLK Command ACT
tRRD
ACT
tRCD
READ
PRE
tRP
ACT
A0-9,11
Xa
Xb
Yb
Xa
A10
Xa
Xb
0
1
Xa
BA0-1
00
01
01
00
DQ
Qb0
Qb1
Qb2
Qb3
Precharge All
READ A READ command can be issued to any active bank. The start address is specified by A0-9(x4), A0-8 (x8), A0-7 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. M inimum delay of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. = MITSUBISHI ELECTRIC
17
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM Multi Bank Interleaving Read (CL=2, BL=4)
CLK Command ACT
tRCD
READ
ACT
tRCD
READ PRE
tRP
ACT
A0-9,11
Xa
Ya
Xb
Yb
Xa
A10
Xa
0
Xb
0
0
Xa
BA0-1
00
00
01
01
00
00
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK Command ACT
tRCD
READ
BL tRP
ACT
A0-9,11
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
00
DQ
Qa0
Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK Command ACT
tRCD
READ
BL
ACT
DQ
CL=2
Qa0
Qa1
Qa2
Qa3
DQ
CL=3
Qa0
Qa1
Qa2
Qa3
internal precharge starts
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
WRITE A WRITE command can be issued to any active bank.The start address is specified by A0-9(x4), A0-8 (x8), A0-7 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. M inimum delay of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the p revious WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. = Write (BL=4)
CLK Command ACT
tRCD
Write
BL
PRE
tRP
ACT
A0-9,11
Xa
Ya
Xa
A10
Xa
0
0
Xa
BA0-1
00
00
tWR
00
00
DQ
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK Command ACT
tRCD
Write
BL tRP
ACT
A0-9,11
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
tWR
00
DQ
Da0
Da1
Da2
Da3 internal precharge starts
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read op eration can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read interrupted by Read (CL=2, BL=4)
CLK Command READ READ READ
A0-9,11
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
DQ
Qa0
Qa1
Qa2
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ] Burst read op eration can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read interrupted by Write (CL=2, BL=4)
CLK Command ACT READ Write
A0-9,11
Xa
Ya
Ya
A10
Xa
0
0
BA0-1
00
00
00
DQM DQ Qa0 Da0 Da1 Da2 Da3
Output disable by DQM
by WRITE
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
[ Read Interrupted by Precharge ] A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Precharge (BL=4)
CLK Command READ PRE
DQ
Q0
Q1
Q2
Command
READ
PRE
CL=2
DQ Q0 Q1
Command
READ PRE
DQ
Q0
Command
READ
PRE
DQ
Q0
Q1
Q2
Command
READ
PRE
CL=3
DQ Q0 Q1
Command
READ PRE
DQ
Q0
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
[ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Terminate (BL=4)
CLK Command READ TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
CL=2
DQ Q0 Q1
Command
READ TBST
DQ
Q0
Command
READ
TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
CL=3
DQ Q0 Q1
Command
READ TBST
DQ
Q0
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write interrupted by Write (BL=4)
CLK Command Write Write Write
A0-9,11
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
DQ
Da0
Da1
Da2
Db0
Dc0
Dc1
Dc2
Dc3
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care". Write interrupted by Read (CL=2, BL=4)
CLK Command ACT Write READ
A0-9,11
Xa
Ya
Yb
A10
Xa
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
don't care
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM . Write interrupted by Precharge (BL=4)
CLK Command ACT Write PRE
tRP
ACT
A0-9,11
Xa
Ya
Xa
A10
0
0
0
0
BA0-1 DQM
00
00
00
00
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK. Write interrupted by Terminate (BL=4)
CLK Command ACT Write TBST Write
A0-9,11
Xa
Ya
Yb
A10
0
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write or Read to another Bank ] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA interrupted by WRITE to another bank (BL=4)
CLK Command Write Write
BL tRP
ACT
A0-9,11
Ya
Yb
tWR
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3 activate
auto-precharge interrupted
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK Command Write Read
BL tRP
ACT
A0-9,11
Ya
Yb
tWR
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3 activate
auto-precharge interrupted
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ] Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA interrupted by READ to another bank (CL=2, BL=4)
CLK Command Read Read
BL tRP
ACT
A0-9,11-12
Ya
Yb
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
auto-precharge interrupted
activate
Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal. Single Write When sigle write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an autorefresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK /CS /RAS /CAS /WE CKE A0-11 BA0-1 minimum tRFC
NOP or DESELECT
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK NOP
/CS /RAS /CAS /WE CKE A0-11 BA0-1
new command X 00
Self Refresh Entry
Self Refresh Exit
minimum tRFC for recovery
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK tIH CKE tIS tIH tIS
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP NOP Standby Power Down
CKE Command
ACT NOP NOP NOP
Activ e Power Down
DQ Suspend by CKE
CLK CKE Command
Write Read
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
DQM CONTROL DQM (U, L) is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQM (U, L) masks input data word by word. DQM (U, L) to Data In latency is 0. During reads, DQM (U, L) forces output to Hi-Z word by word. DQM (U, L) to output Hi-Z latency is 2. DQM Function
CLK Command DQM(U, L)
Write Read
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM(U, L)=H
disabled by DQM(U, L)=H
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Conditions with respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5 50 Ta = 25'C 1000 0 ~ 70 -65 ~ 150 Unit V V V V mA mW 'C 'C
Supply Voltage for Output with respect to VssQ Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature with respect to Vss with respect to VssQ
RECOM M ENDED OPERATING CONDITIONS
(Ta=0 ~ 70'C, unless otherwise noted)
Limits Symbol Vdd Vss VddQ VssQ VIH *1 VIL *2 Parameter Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs Min. 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 Vdd+0.3 0.8 Unit V V V V V V
NOTES) 1. VIH(max)=5.5V AC f or pulse width less than 10ns. 2. VIL(min)=-1.0V AC f or pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin Input Capacitance, I/O pin VI=1.4v f=1MHz VI=200mVrms Test Condition Min. 2.5 2.5 2.5 4.0 Max. 3.8 3.8 3.5 6.5 Unit pF pF pF pF
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
ITEM
operating current
tRC=min, tCLK =min, BL=1 , CL=3 single bank operation Icc1 Symbol Organization x4 x8 x16
tCLK = 15ns CKE = H VIH > Vcc - 0.2V VIL < 0.2V CLK = L & CKE = H VIH > Vcc - 0.2V VIL < 0.2V all input signals are fixed.
Limits (max.) -6 75 75 85 20 -7 70 70 80 20 -8 70 70 80 20
Unit
mA
precharge standby current in Non Power down mode
/CS > Vcc -0.2V
Icc2N
x4/x8/x16
mA
Icc2NS
x4/x8/x16
15
15
15
mA
precharge standby current in Power down mode
/CS > Vcc -0.2V
tCLK = 15ns CKE = L CLK = L CKE = L CKE = H, tCLK=15ns
Icc2P
x4/x8/x16
2
2
2
mA
Icc2PS Icc3N Icc3NS
x4/x8/x16 x4/x8/x16 x4/x8/x16 x4
1 30 25 90 90 100 130 1 0.5
1 30 25 70 70 80 110 1 0.5
1 30
mA
active standby current
CKE = H, CLK=L
All Bank Active tCLK = min BL=4, CL=3
mA 25 70 70 80 110 1 0.5 mA mA mA mA
burst current
Icc4
x8 x16
auto-refresh current self-refresh current
tRC=min, tCLK=min
Icc5 Icc6
x4/x8/x16 x4 6,7,8 /x8 /x16 6L,7L,8L
CKE < 0.2V
NOTE) 1. Icc(max) is specif ied at the output open condition. 2. Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) IOZ II Parameter High-Level Output Voltage (DC) Low-Level Output Voltage (DC) Off-state Output Current Input Current Test Conditions IOH=-2mA IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V -5 -5 2.4 0.4 5 5 Limits Min. Max. Unit V V A A
MITSUBISHI ELECTRIC
32
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
AC TIM ING REQUIREMENTS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V
Limits Symbol Parameter Min. tCLK CLK cycle time CL=2 CL=3 tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle time Refresh Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act delay Mode Register Set Cycle time Refresh Interval time (all inputs) (all inputs) 10 7.5 2.5 2.5 1 1.5 0.8 67.5 75 20 45 20 12 15 10 64 100K 10 -6 Max. Min. 10 10 3 3 1 2 1 70 80 20 50 20 12 20 10 64 100K 10 -7 Max. Min. 13 10 3 3 1 2 1 70 80 20 50 20 12 20 10 64 100K 10 -8 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Unit
CLK
1.4V AC timing is referenced to the input signal crossing through 1.4V.
Signal
1.4V
MITSUBISHI ELECTRIC
33
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted) SWITCHING CHARACTERISTICS
(Ta=0 - 70'C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Limits Symbol Parameter Min. CL=2 tAC Access time f rom CLK Output Hold time f rom CLK Delay , output lowimpedance f rom CLK Delay , output highimpedance f rom CLK CL=3 CL=2 CL=3 3 2.7 0 2.7 5.4 -6 Max. 6 5.4 3 3 0 3 6 Min. -7 Max. 6 6 3 3 0 3 6 Min. -8 Max. 7 6 ns ns ns ns ns ns *1 Unit Note
tOH
tOLZ tOHZ
NOTE) 1. If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
Output Load Condition
VOUT 50pF
CLK
1.4V
DQ
1.4V
Output Timing Measurement Reference Point
CLK tOLZ DQ
1.4V
1.4V
tAC
tOH
tOHZ
MITSUBISHI ELECTRIC
34
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Burst Write (Single Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT #0
WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
35
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Burst Write (Multi Bank) [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC tRC
/CS
tRAS tRRD tRP
/RAS
tRCD tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
PRE#0
ACT #0
WRITE#0 ACT#1
PRE#0
WRITEA#1 (Auto-Precharge)
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
36
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Burst Read (Single Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRAS tRP tRAS
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ#0
PRE#0
ACT #0
READ#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
37
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Burst Read (Multi Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC tRC
/CS
tRRD tRAS
/RAS
tRCD tRCD tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READA#0 ACT#1 READA#1
ACT #0
READ#0 ACT #1
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
38
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Write Interrupted by Write [BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
0
1
0
0
1
D0
D0
D0
D0
D0
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
WRITE#0 WRITEA#1 interrupt interrupt same other bank bank
WRITE#0 interrupt other bank
PRE#0 ACT #1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
39
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Read Interrupted by Read [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
1
1
0
1
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READ#0 ACT#1
READ#1 interrupt other bank
READA#1 READ#0 interrupt interrupt same bank other bank
ACT #1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X X Y Y Y
X
X
X
X
0
1
0
1
1
1
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE#0 READ#1 ACT#1
WRITE#1
PRE#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Write / Read Terminated by Precharge [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRC
/CS
tRP tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y X Y X
X
X
X
X
X
X
0
0
0
0
0
0
0
D0
D0
Q0
Q0
ACT#0
WRITE#0
PRE#0 ACT#0 Terminate
READ#0
PRE#0 ACT#0 Terminate
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
42
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y Y Y
X
X
0
0
0
0
0
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0
WRITE#0 TERM READ#0 TERM
WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Single Write Burst Read [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y Y
X
X
0
0
0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 READ#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
44
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Power-Up Sequence and Intialize
CLK
200s
/CS
tRP tRFC tRFC tRSC
/RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
NOP Power On PRE ALL REFA REFA REFA MRS ACT #0
MA
X
0
X
0
X
0
0
Minimum 8 REFA cycles
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
45
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Auto Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y
X
X
0
0
D0
D0
D0
D0
PRE ALL
REFA
ACT#0
WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
46
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Self Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
tRFC
/CS
tRP
/RAS /CAS /WE CKE DQM A0-8, A10 A9,11 BA0,1 DQ
X
X
X
0
PRE ALL Self Refresh Entry All banks must be idle before REFS is issued.
Self Refresh Exit
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
47
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
CLK Suspension [CL=2, BL=4]
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X Y Y
X
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 internal CLK suspended
READ#0
internal CLK suspended
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
48
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK /CS /RAS /CAS /WE
Standby Power Down Active Power Down
CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X
X
X
0
PRE ALL
ACT #0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
49
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Revison History
Rev.
1.0 2.0
Date
Jun '99 July '99 -1st edition
Description
-single write mode is added -Icc5 for -6 is changed form 110mA to 130mA -tRFC is added -tRSC is changed -tSRX and tPDE are removed
3.0
Oct. '99
3.1
Oct. '99
-tWR is changed to 12ns
MITSUBISHI ELECTRIC
50
MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x
4-BIT) 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum ef f ort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury , f ire or property damage. Remember to giv e due consideration to saf ety when making y our circuit designs, with appropriate measures such as (i) placement of substitutiv e, auxiliary circuits, (ii) use of non-f lammable material or (iii) prev ention against any m alf unction or mishap.
Notes regarding these materials
1.These materials are intended as a ref erence to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not conv ey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party . 2.Mitsubishi Electric Corporation assumes no responsibility f or any damage, or inf ringement of any thirdparty 's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.All inf ormation contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of t hese materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improv ements or other reasons. It is theref ore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor f or the latest product inf ormation bef ore purchasing a product listed herein. The inf ormation described here may c ontain technical inaccuracies or ty pographical errors. Mitsubishi Electric Corporation assumes no responsibility f or any damage, liability , or other loss rising f rom these inaccuracies or errors. Please also pay attention to inf ormation published by Mitsubishi Electric Corporation by v arious means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4.When using any or all of the inf ormation contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to ev aluate all inf ormation as a total sy s t em bef ore making a f inal decision on the applicability of the inf ormation and products. Mitsubishi Electric Corporation assumes no responsibility f or any damage, liability or other loss resulting f rom the inf ormation contained herein. 5.Mitsubishi Electric Corporation semiconductors are not designed or manuf actured f or use in a dev ice or system that is used under circumstances in which human lif e is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein f or any specif ic purposes, such as apparatus or systems for transportation, v ehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approv al of Mitsubishi Electric Corporation is necessary t o reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license f rom the Japanese gov ernment and cannot be imported into a country other than the approv ed destination. Any div ersion or reexport contrary t o the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor f or f urther details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
51

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